`timescale 10ns/1ps

module divider_test;

	reg iClk; 			// input clock
	reg iReset; 			// reset signal
	reg iReady; 			// indicates inputs are ready
	wire oDone; 			// indicates that the result is ready

	reg [15:0] iDividend; 	// 16-bit Dividend [15:0]
	reg [7:0] iDivisor; 		// 8-bit Divisor [7:0]
	wire [7:0] oQuotient; 	// 8-bit Quotient [8:0]
	wire [7:0] oReminder; 	// 8-bit Reminder [7:0]

	divider U2(.*);

	initial
	begin
		iClk=1'b0;
		forever #0.5 iClk=~iClk; //(단위시간)*0.5 동안의 시간마다 클록의 값을 반전.
	end

	initial
	fork
		#0 {iReset, iReady}<=2'b10;
		#0 iDividend <= 16'b0000_0000_0000_0111;
		#0 iDivisor <=8'b0000_0010;
		#2 iReset <= 1'b0;
		#10 iReady <= 1'b1;
		
		
		#20 iDividend <= 16'b0000_1010_0000_0000;
		#20 iDivisor <=8'b0010_0000;
		#20 iReady <= 1'b0;
		#23 iReady <= 1'b1;
		
		#30 iDividend <= 16'b1111_1111_1100_0000;
		#30 iDivisor <=8'b1111_0000;
		#30 iReset <=1'b1;
		#31 iReset <=1'b0;
		
		#40 iDividend <= 16'b0000_0000_0000_0111;
		#40 iDivisor <=8'b1111_1101;
		
		#50 iDividend <= 16'b1111_1111_1111_1001;
		#50 iDivisor <=8'b0000_0011;
		
		#60 iDividend <= 16'b1111_1111_1111_1001;
		#60 iDivisor <=8'b1111_1101;
		
		#70 iDividend <= 16'b0000_0011_0000_0000;
		#70 iDivisor <=8'b0000_0001;
		
		#80 iDividend <= 16'b0000_1010_0000_0000;
		#80 iDivisor <=8'b0001_0000;
		
		#90 iDividend <= 16'b0000_0000_0000_0000;
		#90 iDivisor <=8'b0000_0000;
	join

endmodule